1. Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly to a triple metal line, one transistor and one capacitor (1T/1C) ferroelectric memory device and a method for fabrication thereof.
2. Background of the Invention
Modern data processing systems require that a substantial portion of the information stored in their memory be randomly accessible to ensure rapid access to such information. Ferroelectric random access memories (FRAMs) have been proposed because of their high-speed operational speeds. FRAMs also exhibit a significant advantage of being non-volatile. This is achieved by the fact that a ferroelectric capacitor includes a pair of capacitor electrodes having ferroelectric material placed in between. FRAMs have two different, stable polarization states, which can be defined with a hysteresis loop by plotting polarization against applied voltage. Ferroelectric memory elements are programmable with less than 5V (flash memory requires about 18 to 22V), have a small access time (less than 40 nsec access time whereas a flash memory requires a few microseconds), and offer virtually an unlimited number of read and write cycles. These memory elements also consume little power and exhibit alpha-particle immunity.
The non-volatile ferroelectric memory device includes a transistor that is electrically connected to an associated ferroelectric capacitor. There are two ways of interconnecting the source of the transistor to the ferroelectric capacitor. One way is through formation of a local metal interconnection, as disclosed in U.S. Pat. No. 5,119,154, the disclosure of which is incorporated herein by reference. An alternative way of interconnecting the source of the transistor to the ferroelectric capacitor is through formation of a contact plug using a conductive material, such as polysilicon or tungsten (W). For a high density, non-volatile ferroelectric memory device, the latter method is preferred in order minimize unit cell size. As a result, a local interconnection between the transistor and the ferroelectric capacitor is made via a contact plug. The disclosures of U.S. Pat. No. 5,854,104 and U.S. Pat. No. 5,591,663 are incorporated herein by reference.
FIGS. 1A to 1E are cross-sectional views of a semiconductor substrate illustrating a process for fabricating a non-volatile semiconductor memory device according to the prior art.
Referring to FIG. 1A, a semiconductor substrate 1 includes thereon an isolation region 2 and a transistor. The transistor includes a gate oxide layer 3, a gate electrode 4, a source region 5a, and a drain region 5b. A bit line 6, which is electrically connected to the source region 5a, is also formed. A borophosphosilicate glass (BPSG) layer 7 is deposited on the resulting structure. Then a titanium dioxide (TiO2) film 8 (about 1,000 angstroms thick), serving as a diffusion barrier layer for a ferroelectric film, is formed by a reactive sputtering method. A contact hole 20 is then formed by using a photolithographic process.
Referring to FIG. 1B, a double-layer film 10, composed of a titanium (Ti) film (about 500 angstroms thick) and a titanium nitride (TiN) film (about 1,000 angstroms thick), and a blanket layer of tungsten (W) 11 (about 5,000 angstroms thick) are formed by a sputtering method in order to fill the contact hole 20. Then the tungsten (W) film 11 and the titanium nitride/titanium (TiN/Ti) double-layer film 10 are etched back by a chemical mechanical polishing (CMP) method to form a contact plug.
Referring to FIG. 1C, a titanium nitride (TiN) film 12 (about 500 angstroms thick) and a platinum (Pt) film 13 (about 500 angstroms thick) are sequentially formed by a sputtering method. Using a patterned resist 9b, the platinum (Pt) film 13 and the titanium nitride (TiN) film 12 are dry etched to form the lower electrode.
Referring to FIG. 1D, a lead zirconate titanate (PZT) film 14 (about 2,000 angstroms thick) is formed on the lower electrode by a sol-gel method, a sputtering method or a metal-organic chemical vapor deposition (MOCVD) method, and is then annealed. A platinum (Pt) film 15 (about 1,000 angstroms thick), a titanium nitride (TiN) film 16 (about 500 angstroms thick), and an aluminum (Al) film 17 (about 1,000 angstroms thick) are sequentially formed on the PZT film 14. These films are dry etched using a high-density plasma system and mask resist 9c to form the ferroelectric capacitor.
After the capacitor is formed in the aforesaid manner, an insulating layer 18 is formed over the resulting ferroelectric capacitor and titanium oxide (TiO2) layer 8, as depicted in FIG. 1E.
According to the above-mentioned method, the formation of the PZT film 14 is preceded by the patterning of the lower electrode. Namely, after the formation of the lower electrode, high temperature annealing at about 600 to 800 degrees C., in an ambient oxygen atmosphere is carried out on the deposited PZT film 14 in order to form a perovskite crystalline. Furthermore, a diffusion barrier layer formed by high temperature annealing above 500 degrees C. in an ambient oxygen atmosphere is required to improve barrier characteristics. The aforementioned high temperature annealing processes cause oxidation at the interface between the lower electrode and the contact plug. Oxidation still occurs at the interface between the titanium nitride (TiN) film and the contact plug due to the diffusion of oxygen through the sidewall of the stacked ferroelectric capacitor. Such oxidation at the interfaces cannot produce a reliable electrical ohmic contact. As a result, it can be very difficult to deliver the stored data in the ferroelectric capacitor to the data line, thereby degrading the performance of the memory device.
Therefore, the present invention was made in view of the above problem and is directed towards providing a non-volatile ferroelectric memory device and a method for fabrication thereof. More particularly, the present invention provides a triple metal line 1T/1C ferroelectric memory device. The present invention also provides a method for the fabrication of the triple metal line 1T/1C ferroelectric memory device.
Preferably, an embodiment of the present invention includes a method for fabricating a ferroelectric device comprising the steps of forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a buried contact plug therein; forming an oxidation barrier layer on the interlayer insulating layer and on the contact plug to prevent oxidation of the contact plug; forming a ferroelectric capacitor and a diffusion barrier layer pattern on the oxidation barrier layer, the ferroelectric capacitor being aligned over the contact plug and the diffusion barrier layer covering the ferroelectric capacitor; and etching the exposed oxidation barrier layer by the diffusion barrier layer pattern.
A feature of the present invention is that an upper electrode of the ferroelectric capacitor is patterned prior to or simultaneously with the patterning of the ferroelectric film and lower electrode. The patterning of the oxidation barrier layer is done after forming the ferroelectric capacitor and after depositing and subsequently high temperature annealing the diffusion barrier layer in an ambient oxygen atmosphere. As a result, a reliable electrical ohmic contact between a buried contact plug and a lower electrode of the ferroelectric capacitor is obtained.
In accordance with the present invention, there is a method provided for fabricating a non-volatile ferroelectric memory device. The method is comprised of forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a buried contact plug therein; forming an oxidation barrier layer on the interlayer insulating layer and the contact plug in order to prevent oxidation of the contact plug; forming a ferroelectric capacitor over the contact plug; forming a diffusion barrier layer on the oxidation barrier layer and on the ferroelectric capacitor; patterning the diffusion barrier layer to cover the ferroelectric capacitor; and etching the exposed oxidation barrier layer by the pattern of the diffusion barrier layer.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a non-volatile triple metal line ferroelectric memory device. The method is comprised of forming a transistor including a gate electrode and source/drain regions on a semiconductor substrate; forming a first interlayer insulating layer over the semiconductor substrate and the transistor; forming a first metal line, which is electrically connected to one of the source/drain regions, on the first interlayer insulating layer; forming a second interlayer insulating layer over the first interlayer insulating layer and the first metal line; forming a contact plug, which is electrically connected to the other of the source/drain regions through the second and first interlayer insulating layers; forming a ferroelectric capacitor, which is electrically connected to the contact plug, on the second interlayer insulating layer; forming a third interlayer insulating layer over the second interlayer insulating layer and the ferroelectric capacitor; forming a second metal line, which is electrically connected to the gate electrode, on the third interlayer insulating layer; forming a fourth interlayer insulating layer over the third interlayer insulating layer and the second metal line; and forming a third metal line, which is electrically connected to the ferroelectric capacitor, on the fourth interlayer insulating layer.
In accordance, still another feature of the present invention, there is provided a triple metal line 1T/1C ferroelectric memory device. The ferroelectric memory device comprises a transistor that has a gate electrode and source/drain regions formed on a semiconductor substrate; a first interlayer insulating layer formed on the transistor and on the substrate; a first metal line, which is electrically connected to one of the source/drain regions, through the first interlayer insulation layer; a second interlayer insulating layer formed on the first interlayer insulating layer and the first metal line; a ferroelectric capacitor, which is electrically connected to the other of the source/drain regions through the contact plug formed in the first and second interlayer insulating layers, formed on the second interlayer insulating layer; a diffusion barrier layer formed on the ferroelectric capacitor; a third interlayer insulating layer formed on the second interlayer insulating layer and the diffusion barrier layer; a second metal line, which is electrically connected to the gate electrode, formed on the third interlayer insulating layer; a fourth interlayer insulating layer formed on the third interlayer insulating layer and the second metal line; and a third metal line, which is electrically connected to the ferroelectric capacitor, formed on the fourth interlayer insulating layer.
The present invention will now be described hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure conveys the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It is also to be understood that when a layer is referred to as being xe2x80x9conxe2x80x9d another layer or substrate, it can be directly on the other layer or substrate or intervening layers may also be present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.
The invention may be understood and its features will become apparent to those skilled in the art by reference to the accompanying drawings.